1) Field of the Invention
The present invention relates to a semiconductor device having a BIST (Built In Self Test) circuit to test a memory (RAM: Random Access Memory) for use in processing incorporated in a data processing system of the semiconductor device, and a testing apparatus for the semiconductor device.
2) Description of the Related Art
As a method for testing a memory of a semiconductor device such as an LSI (Large Scale Integration) or the like, there is a testing method using a BIST (Built In Self Test) circuit, for example (refer to patent documents 1 through 4 mentioned below).
A semiconductor device with the BIST circuit has a structure shown in, for example, FIG. 7. As shown in FIG. 7, the semiconductor device 100 comprises a memory (for example, a RAM: Random Access Memory) 101 incorporated in a data processing system of the semiconductor device 100 to be tested, a BIST circuit 102, a control circuit 103, a checker 104, and a latch array for storing data 105. A tester 110 is detachably connected from the outside to the semiconductor device 100.
The memory (hereinafter referred as a RAM) 101 functions as a memory of the semiconductor device 100, configured as a so-called DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory) or the like.
The BIST circuit 102 is a circuit for making a built-in self test on the RAM 101. The BIST circuit 102 issues, to a RAM 101, a test pattern including data to be written into the RAM 101 and an address of a position (that is, an address in the RAM 101) at which the data is to be written, prepares an expected value of the test pattern, and transmits the expected value to the checker 104 to be described later.
The control circuit 103 is a circuit for controlling the BIST circuit 102. Practically, the control circuit 103 controls a start/end of the test by the BIST circuit 102.
After a writing into the RAM 101 on the basis of the test pattern generated by the BIST circuit 102, the checker 104 compares data read out from the RAM 101 with an expected value corresponding to the test pattern prepared by the BIST circuit 102, and transmits a result of the comparison to the latch array for storing data 105 to be described later.
A result of the comparison transmitted from the checker 104 to the latch array for storing data 105 represents whether or not the data read out from the RAM 101 agrees with the expected value as data of 1 or 0, which is generated for each test pattern generated by the BIST circuit 102, and is transmitted to the latch array for storing data 105. When the data read out from the RAM 101 agrees with the expected value, “1” is transmitted to the latch array for storing data 105 as a result of the comparison. When the data does not agree with the expected value, “0” is transmitted.
The latch array for data storing 105 stores a result of the comparison transmitted from the checker 104, which is a so-called first-in first-out memory latch array.
The tester 110 is detachably connected to the outside of the semiconductor device 100 to take out results of the comparison stored in the latch array for storing data 105.
In the known semiconductor device 100 structured as above, the tester 110 is connected to the semiconductor device 100, and the control circuit 103 controls the BIST circuit 102 to start the test. The BIST circuit 102 successively issues test patterns to the RAM 101, writes a plurality of patterns in the RAM 101, prepares an expected value for each of the test patterns, and transmits the expected value to the checker 104. The checker 104 compares data read out from the RAM 101 with the expected value transmitted from the BIST circuit 102, and transmits whether or not the data agrees with the expected value as a result of the comparison (here, “1” in the case where the data agrees with the expected value or “0” in the case where the data does not agree with the expected value) to the data array for storing data 105. The result of the comparison is stored in the latch array for storing data 105. The tester 110 takes out results of the test (results of comparison) stored in the latch array for storing data 105, and evaluates the results, thereby to test the RAM 101.
In the known semiconductor device 100 shown in FIG. 7, it is general that the tester 110 is manufactured in a technology in older generation than the semiconductor device 100. Accordingly, the processing speed of the tester 110 is lower than the processing speed of the semiconductor device 100. Even if a device (MPU: Micro Processing Unit, CPU: Central Processing Unit or the like) of the semiconductor device 100 to be tested is operated at fast clock cycle, the processing speed of a device (MPU, CPU or the like) of the tester 110 cannot catch up with the clock cycle of the semiconductor device 100. As a result, the tester 110 cannot read out results of comparison written in the latch array for data storing 105 at the fast clock cycle of the semiconductor device 100. In guaranteeing the product operations, it is an important element in the test on the RAM 101 to shift the addresses in the RAM 101 one after another, and successively read and write the data. In the known semiconductor device 100 shown in FIG. 7, there is no alternative but to adjust the processing speed of the device of the semiconductor device 100 to the processing speed of the tester 110 and make the test at the lower clock cycle. It is thus impossible to test the RAM 101 at the original processing speed of the semiconductor device 100.
Even if a tester 110 having a device (a CPU or the like) operable at a processing speed equivalent to that of the semiconductor device 100 is prepared using a technology equivalent to that used to manufacture the semiconductor device 100, such tester 110 would be very costly. Additionally, it is not realistic to prepare a tester equivalent to the semiconductor device each time the semiconductor device to be tested is developed.
In the known semiconductor device 100 shown in FIG. 7, the latch array for storing data 105 storing results of comparison obtained by the checker 104 has generally a smaller capacity than the RAM 101. Accordingly, there is a case where the latch array 105 cannot store all results of the test successively made on the whole RAM 101. It is important in the test on the RAM 101 in order to guarantee the product operation to successively carry out reading and writing of data at all addresses in the RAM 101. In the above latch array for storing data 105, it is necessary to divide the test on the RAM 101 into parts and make the test plural times, which is an obstacle to a guarantee of reliable operations of the product.
In the test of the semiconductor device 100, it is very effective to investigate in which physical position (i.e., at which address) of the cell array of the RAM 101 a failure occurs, that is, it is very effective to prepare a bit failure map. However, the first-in first-out latch array for storing data 105 cannot store a result of comparison with an address designated, thus it is impossible to prepare a bit failure map at the time of a testing operation of the RAM 101.
Accordingly, there is proposed a technique solving the above problem by newly providing, instead of the latch array for storing data 105, a memory (RAM) equivalent to the RAM 101 outside the semiconductor device 100 to store results of comparison obtained by the checker 104 therein (refer to patent documents 1 through 4 below, for example).
[Patent Document 1] Japanese Patent Laid-Open Publication No. 2002-298598
[Patent Document 2] Japanese Patent Laid-Open Publication No. 11-238400
[Patent Document 3] Japanese Patent Laid-Open Publication No. 10-302499
[Patent Document 4] Japanese Patent Laid-Open Publication No. 2002-133897
If a RAM having a performance equivalent to that of the RAM 101 is newly provided outside the semiconductor device 100 in order to store results of the test (results of comparison transmitted from the above checker 104), it would cost more than the case where the above latch array for storing data 105 is provided inside the semiconductor device 100, of course.
When the semiconductor device 100 is an MPU, CPU or the like of a server or a personal computer and the RAM 101 to be tested is an SRAM, the cost of the test further increases because the SRAM is very expensive.
RAMs provided as memories in semiconductor devices such MPU, CPU or the like are extensively developed, aimed at high-speed and high-density (large-capacity). If a RAM equivalent to a newly developed RAM is prepared for the test each time a semiconductor device (MPU, CPU or the like) having such the newly developed RAM is developed, the cost would be further increased.
Instead, when a RAM for storing results of the test is provided outside the semiconductor device 100, it is necessary to newly provide an interface and a control system for connecting the RAM to the semiconductor device 100, which causes complication of the system and an increase in cost.
When a built-in self test is made on a memory (RAM) of a semiconductor device using a BIST circuit, the memory for storing results of the test (results of comparison transmitted from the checker 104) has to be configured so that the stored results of the test can be accurately read out, as a matter of course.
However, the latch array for storing data 105 provided in the known semiconductor device 100 shown in FIG. 7 and the techniques disclosed in the patent documents 1 through 4 do not have any means of certainly reading out results of the test written in the memory.